Levandor

hardcut Topics

7 min read

For Agents

Living index of themes for this project. Each H2 is a topic; bullets are wikilinks to related notes. Updated by obsidian-documenter when documenting work. Read by historian at bootstrap. Topics kept alphabetical.

Bench Rig & Instruments

  • inventory — ⭐ the vault-level parts inventory this note graduated into (2026-09-02). All 26 line items of order H26/7333913 (not just the 9 hardcut uses), the two amendments missing from the cart XML, and the confirmed-absent list that gates this bench: no bench PSU, no oscilloscope (the SPS-C3206 at 37 900 Ft and DSO2D10 at 111 000 Ft were in the cart and cut before placing), no ceramic caps, and no 12 V 9 Ah AGM battery (100.459.79, 7 756 Ft) — which this bench needs because a coil primary at 0.9–1.1 Ω draws 6–12 A dwell and the 12 W adapters on hand collapse. Also the cikkszám = product URL with dots rule
  • hardcut-bench-inventory — ⚠️ hardcut-scoped subset, superseded for global purposes by inventory (2026-09-02) — records only 9 of the order’s 26 line items. Still owns the bench-substitute distinction. What is physically owned for the bench, with HESTORE cikkszámok. Everything came in one order (H26/7333913, placed 2026-08-08, arrived 2026-08-11; cart XML at /Users/levander/Downloads/hestore_20260808.xml): the analyzer + 4 clip hooks, and the Task 8 parts 74HC14-CF ×2 / 74HC74 ×2 / IRLZ44NPBF ×5 + BB-102 breadboard + RPACK-600 resistor kit + SS-5GL ×2. ⚠️ These are bench substitutes — the production parts (74LVC1G17Q, BSS806N, LM74700-Q1/SMBJ33A/LM5164-Q1/AP2112K-3.3) were never bought
  • 2026-08-29-logic-analyzer-toolchain — the analyzer itself: Logic-24M-8CH, a CY7C68013A (FX2LP) 8 ch / 24 MHz Saleae clone, driver fx2lafw. Probe map for Task 9: emulator GPIO 4 = IGt, GPIO 5 = IGf, main ESP32 GPIO 15 = flip-flop D, 74HC74 pin 5 = Q, plus node A. Digital ignition timing only — not bus protocol decoding
  • Task 8: Breadboard the front end, flip-flop and shunt — the 74HC14 / 74HC74 / IRLZ44N breadboard the instruments clip onto

Cross-Project

  • lightaim — sibling ESP32-S3 project on the same vehicle: joystick-aimed light (velocity-control servo), bench-working 2026-08-12. Read 2026-08-12-lightaim-bench-bringup before flashing any S3 for hardcut — it has the reusable toolchain/flash gotchas: uvx --from platformio needs --with pip, the S3 bootloader goes at 0x0 (not 0x1000), only the CH343 UART port (1a86:55d3) can flash a running chip, and LEDC caps at 14-bit duty resolution
  • cluzter — wiring-diagram editor for the same vehicle; this project’s signal table is one of its wire-data sources
  • cluzter-wiring-gotchas — the JIS B (black) vs Bl (blue) trap that applies to every colour code used here
  • pipeline — the jot → WireViz pipeline where this car’s harnesses were first captured
  • kb-agent-api — the homelab knowledgebase API for querying the OCR’d Vitara/Sidekick manuals

Design

  • hardcut — project entry point: what it is, status, the three measurement gates, the flip-flop interlock, signals, calibration defaults, build order, risks
  • 2026-07-29-hardcut-design — the full design: ignition-cut strategy, why fuel cut is the wrong lever on this ECM, the consecutive-miss-counter insight, hardware, test plan
  • 2026-08-08-hardcut-plan — the 14-task TDD implementation plan; decision logic is pure C++ in lib/core/ with 28 native unit tests, so Tasks 1–5 and 11 need no hardware at all

Measurement Gates (do these before touching the car)

  • hardcut — 🔴 all three, in order, with the formulas. Gate 1: count ECM coupler cavities (expect 22-pin A + 26-pin B) + VIN 8th digit — every pin number is Vitara-manual-sourced, a different count means stop. Gate 2: the 220 Ω source-impedance test on IGt, R_out = (V1−V2)/(V2/220), choose R_sh ≤ R_out/6 — R_out < 60 Ω abandons the parallel shunt for a series interrupt. Gate 3: stall test to replace the placeholder 2,500 rpm launch limit
  • Task 13: Car measurement gate — Gates 1 and 2, read-only, nothing cut
  • Task 14: Car commissioning — Gate 3, then main limiter at 5000 first, then the two-step

Safety Architecture

  • hardcut — the 74HC74 D flip-flop clocked on IGt’s falling edge: the plan supersedes the design’s software mid-dwell check with hardware, so the one engine-destroying bug (asserting the shunt while IGt is high fires the plug at a random advance angle) becomes physically unreachable. Passive fail-safe is 100 kΩ gate pull-downs = stock car when unpowered/hung
  • Interlocks — VSS stationarity is the load-bearing interlock, not the brake (the stop-light switch closes in the first millimetre of travel, so it proves intent only). A failed-open VSS reed reads as stationary
  • 2026-08-29-logic-analyzer-toolchain — the instrument that proves the two safety claims in hardware: that no run of suppressed events exceeds 5, and that Q only ever moves on IGt’s falling edge while D may change at any time
  • Task 3: Cut patterns and the run cap — MAX_CONSECUTIVE_CUTS = 5 enforced in exactly one place, after the generator; test_run_cap_never_exceeded_any_config sweeps 3 modes × 21 cluster values × 21 ratios × 3000 events and is re-verified on the logic analyzer (Task 9) and against a real igniter (Task 10)

Toolchain

  • 2026-08-29-logic-analyzer-toolchain — macOS capture toolchain decision (verified 2026-08-29): sigrok-cli + Surfer, NOT PulseView. sigrok-cli 0.7.2 / libsigrok 0.5.2 / libsigrokdecode 0.5.3 are native arm64 bottles via arm64_tahoe; surfer 0.7.0 is bottled too. PulseView is not in Homebrew at all and sigrok.org’s macOS nightly DMGs 404 — no macOS binary since the 2020 release. Ruled out: DSView (x86-only, 2023) and ngscopeclient (native arm64 as of v0.2.2 / 2026-08-20 but no fx2lafw driver — scopehal#270, #16; the one to watch). NOT ruled out: Saleae Logic 2 — see below
  • ❓ Open Question: Saleae Logic 2 — untested, try it first — UNTESTED, and worth trying before assuming sigrok is the only path. The clone’s EEPROM reports VID 0x0925 / PID 0x3881, the original 2008-era Saleae Logic’s own USB ID — that is what “Saleae kompatibilis” means. libsigrok’s src/hardware/fx2lafw/api.c files six known clones under that ID, and the FX2 has no flash (firmware loads to RAM at plug-in, so whichever host connects first uploads its own — nothing to undo). Saleae’s docs still say the original Logic “is supported on all releases”, and the clone-resistance that exists applies to post-Oct-2022 hardware revisions, not this ID. Caveats, both stated neutrally: it’s a bare FX2 wearing the ID so the handshake is unverified (community reports mixed), and the EULA restricts the software to Saleae-made hardware — the call is the user’s. Logic 1.x is not the fallback: deprecated at 1.2.40, Logic-1.2.40-MacOS.dmg is Intel-only (Rosetta) and that version removed the Decoded Protocols Panel
  • ⚠️ Gotchas — two traps. (1) sigrok-firmware-fx2lafw is NOT in Homebrew; the FX2 has no onboard flash and re-loads its blob on every plug-in — unpack sigrok-firmware-fx2lafw-bin-0.1.7.tar.gz into ~/.local/share/sigrok-firmware/ (libsigrok’s search order per src/resource.c: $SIGROK_FIRMWARE_DIR → $SIGROK_FIRMWARE_PATH → g_get_user_data_dir()/sigrok-firmware → system dirs). (2) Never capture at 24 MHz — no capture memory, streams 1 byte/sample over USB 2.0 regardless of channels enabled, so it drops samples silently at the bulk ceiling. Use 1 MHz: 1 µs resolution at 1 MB/s, ~1000× finer than 200 sparks/sec needs
  • Toolchain — the ESP32-side toolchain traps that apply to the same bench (uvx --from platformio needs --with pip; Arduino core is 2.0.17, not 3.x)

Vehicle Wiring

  • 2026-07-29-hardcut-design — the signal table: IGt (Orange), IGf (Bl/G, ECM B5), igniter +B (B/W), coil primary − (Br/W), brake switch (Green/White), VSS (Yellow, ECM A7), with measured voltages

Graph View